Our Clients

MixSignal Design, LLC is an analog and mixed-signal design service house and IP provider, specialized on SerDes PHY and PLL's. The partners of MixSignal Design each brings more than 20 years of design and development experience in various disciplines of electronics engineering.

Our focus has been on the high speed serial interfaces PHY. We have implemented variety of different analog and digital architectures in our physical layer transceiver designs based on the speed and specification requirements. Our designs have been manufactured in different CMOS process foundries with geometries ranging from 0.18 um to 28 nm.

Our experience spans over a wide range of functions and process technologies. Our thorough knowledge of design trade-offs at both the system and circuit level, have allowed us to deliver many successful silicon proven designs. Our design methodology includes comprehensive system level behavioral modeling and simulation for architectural refinement before committing to circuit design followed by layout and post layout extraction and verification.

Below is a summary of our design activities in different grouping:

• SerDes PHY with data rates ranging from 1 to 14 Gb/s.
• Standards; SATA, PCIE, SGMII, XAUI, 10GBASE-KX4, 10GBASE-KR, XFI.
• Multi-Standard, wide range data rate PHY's for FPGA's.
• Wide variety of low noise clock multiplying PLL's and Phase aligning DLL's.
• Processes; 0.18-0.11 um, 90-28 nm.
• Foundries; TSMC, SMIC, UMC, Toshiba.

Our services to our customers are very flexible ranging from hard macro IP licensing, complete custom design and development with technology transfer or joint design and development.

We will be supporting our designs up to any stage of the prototyping and production that customer requires. Including and not limited to, integration to the larger customer’s chip, bench evaluation, test plans and test board design, characterization, and support for production.

We also offer reusable and general purpose SerDes platforms for SerDes analysis, evaluation and validation. Please click here for a Presentation on SerDes Platform.